Chemical Mechanical Polishing (CMP) is a part of the chip fabrication process that requires a uniform distribution of metal and silicon over the surface of the chip. To achieve this distribution, pieces of interconnect (metal or silicon) must be inserted into available spaces in low-density regions of the chip. This interconnect insertion is called dummy metal filling or simply dummy filling, and the inserted interconnect is called dummy metal. Dummy metal is typically not allowed to touch or otherwise intersect with any objects in the design.
Most fabrication processes require a minimum density for the interconnects on each layer of a multi-layer chip design. The interconnect density for a region is the sum total of the area of all interconnects in that region divided by the area of the region. Fabrication processes typically partition each layer of the design into rectangular regions, called tiles, and specify that the interconnect density of each tile meet a minimum density requirement.
The process of determining the number and placement of dummy metal is typically preformed by a dummy fill software tool after routing and timing closure during chip design flow. The dummy fill tool operates on a design database that stores the design data for the integrated circuit, and determines whether each tile has an interconnect density equal to or greater than the specified minimum density. If the interconnect density does not meet the minimum density, then the dummy fill tool inserts pieces of dummy metal in free regions of the tile.
The time it takes the dummy fill tool to complete its task is dependent upon the complexity of the integrated circuit design, and correspondingly, the size of the design database. For a design of average complexity, the runtime for the dummy fill tool would be approximately 3-4 hours. With today's new process technologies and increasingly complex designs, the dummy fill tool may have a runtime of up to 30 hours.
The problem is that once a design has almost reached completion, a customer may request changes to the design in the form of engineering change orders (ECO). Once implemented, an ECO may change the locations of objects in the design. And even though most ECO make small incremental changes and 99.9 percent of the design may be left unchanged, the results of the dummy fill tool are thrown out, and the dummy fill tool is rerun in order to ensure that no dummy metal intersects with any of the design objects. Requiring another run of the dummy fill tool is problematic because it may delay completion of the design by another 30 hours. In addition, if more than one ECO is received, multiple runs will be required: one for each ECO. Such an iterative process can significantly impact the design schedule and result in cost overruns.
Accordingly what is needed is a method for inserting dummy metal into an integrated circuit design after an ECO without requiring reruns of the dummy fill tool. The present invention addresses such a need.